Assistant Professor  

Department of Computer Science, City University of Hong Kong, Tat Chee Ave, Kowloon, Hong Kong
Email: jasonxue at cityu.edu.hk Office: Y6428 Phone: 2788 9815

Research Interests

Teaching

Potential Final Year Project:
  1. Parallel Programming using CELL processor from Play Station 3
  2. Defense Against Key Logger Attacks
  3. Automatic Business card matching using Image Recognition
  4. Parallel Protein Identification using Mass Spectrum Data

Publications

    Journal Papers       

  1. C. Xue, J. Hu, Z. Shao, and E. H.-M. Sha, "Iterational Retiming with Partitioning: Loop Scheduling with Complete Memory Latency Hiding"   Accepted for publication in to ACM Transaction on Embedded Computing System (TECS), Jan 2008.


  2. Q. Zhuge, C. Xue, M. Qiu, J. Hu and E. H.-M. Sha, "Timing Optimization via Nest-Loop Pipelining Considering Code Size"   in Journal of Microprocessors and Microsystems, Volume 32, Issue 7, October 2008, Pages 351-363.


  3. C. Xue, Z. Jia, Z. Shao, M. Wang, and E. H.-M. Sha, "Optimize Address Assignment with Array and Loop Transformation for minimizing schedule length"   in IEEE Transaction on Circuits and System (TCAS), 55(1), February 2008, pp 367-377.


  4. C. Xue, Z. Shao, Q. Zhuge, B. Xiao, M. Liu, and E. H.-M. Sha "Optimizing Address Assignment for Scheduling DSPs with Multiple Functional Units," in IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 53, No. 9, pp. 976 - 980, September 2006.


  5. C. Xue, Z. Shao, and E. H.-M. Sha, "Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping"  in Journal of VLSI Signal Processing Systems (JVLSI), Vol. 47, No. 2, May 2007, pp. 153 - 167.


  6. Z. Shao , C. Xue , Q. Zhuge, M. Qiu, B. Xiao and E. H.-M. Sha, "Security Protection and Checking for Embedded System Integration Against Buffer Overflow Attacks via Hardware/Software" in  IEEE Transactions on Computers (TC), Vol. 55, No. 4, pp. 443-453, Apr. 2006.

  7. Z. Shao, C. Xue, Q. Zhuge, B. Xiao and E. H.-M. Sha, "Loop Scheduling with Timing and Switching-Activity Minimization for VLIW DSP" in  ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 1, pp. 165-185, Jan. 2006.

  8. C. Xue, Z. Shao, M. Liu, M. Qiu, E. H.-M. Sha, " Optimizing Parallelism for Nested Loops with Iterational and Instructional Retiming," Accepted for publication in Journal of Embedded Computing (JEC), 2006.

  9. Z. Shao, M. Wang, Y. Chen, C. Xue, M. Qiu, L. T. Yang, E. H.-M. Sha, "Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems," Accepted for publication in IEEE Transactions on Circuits and Systems II (TCAS-II), 2006.


  10. M. Qiu, Z. Jia, C. Xue, Z. Shao and E. H.-M. Sha " Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP ," Accepted for publication in The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), 2006.

  11. M. Qiu, C. Xue, Z. Shao, M. Liu and E. H.-M. Sha, " Energy Minimization for Heterogeneous Wireless Sensor Networks," Accepted for publication in Journal of Embedded Computing (JEC), 2006.

  12. Q. Zhuge, C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, "Design Optimization and Space Minimization Considering Timing and Code Size via Retiming and Unfolding," in Journal of Microprocessors and Microsystems, Vol. 30, Issue 4, June 2006, pp. 173-183.


  13. Z. Shao, Q. Zhuge, M. Liu, C. Xue, E. H.-M. Sha and B. Xiao, ``Algorithms and Analysis of Scheduling for Loops with Minimum Switching", Accepted for Publication in International Journal of Computational Science and Engineering, Vol. 2, 2006.

  14. Z. Shao , J. Cao, K. C. C. Chan, C. Xue , and Edwin H.-M. Sha, "Hardware/software Optimization for Array & pointer Bound Checking Against Buffer Overflow Attacks Accepted for publication in Journal of Parallel and Distributed Computing (JPDC) Special issue on Security in Grid and Distributed Systems, Volume 66, Issue 9, Pages 1129-1136, September 2006.

  15. Z. Shao, Q. Zhuge, C. Xue and E. H.-M. Sha, ``Efficient Assignment and Scheduling for Heterogeneous DSP Systems", in IEEE Transaction on Parallel and Distributed Systems (TPDS), pp. 516-525, Vol. 16, No. 6, June, 2005.

 Submitted Journal Papers

  1. C. Xue, Z. Shao, Q. Zhuge, M.K. Qiu, and E. H.-M. Sha, "Register and Memory Sensitive Loop Scheduling and Partitioning"  Submitted to IEEE Transaction on Parallel and Distributed Computing (TPDS).


Conference Papers

  1. T. Liu, M. Li and C. Xue, "Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking"   Accepted for publication in 15th IEEE Real-Time and Embedded Technology and Applications Symposium, (RTAS 2009), pp 35-44, San Francisco, USA, Apr. 2009.


  2. Y. Zhao, C. Xue, M. Li and B. Hu, "Energy-aware Register File Re-Partitioning for Clustered VLIW Architectures"   Accepted for publication in 14th Asia and South Pacific Design Automation Conference, (ASPDAC 2009), Yokohama, Japan, Jan 2009.


  3. C. Xu, C. Xue, B. Hu and E. H.-M. Sha, "Computation and Data Transfer Co-Scheduling for Interconnection Bus Minimization"   Accepted for publication in 14th Asia and South Pacific Design Automation Conference, (ASPDAC 2009), Yokohama, Japan, Jan 2009.


  4. J. Hu, C. Xue, M. Qiu, W. Tseng, C. Xu, L. Zhang, and E. H.-M. Sha, "Minimizing Transferred Data for Code Update on Wireless Sensor Network"   Accepted for publication in Third International Conference on Wireless Algorithms, Systems, and Applications, (WASA 2008), pp 349-360. Oct 2008.


  5. C. Xue, Z. Yuan, G. Xing, Z. Shao, and E. H.-M. Sha, "Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems"   Accepted for publication in The 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp 237-246. Aug 2008.


  6. M Qiu, J. Wu, C. Xue, J. Hu, W. Tseng, and E. H.-M. Sha, "Loop Scheduling and Assignment to Minimize Energy while Hiding Latency for Heterogeneous Multi-Bank Memory"   Accepted for publication in The 18th IEEE International Conference on Field Programmable Logic and Applications (FPL), Heidelburg, German, Sep, 2008.


  7. C. Xue, E. H.-M. Sha, Z. Shao and M. Qiu `` Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints '' Accepted in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) , Munich, Germany, Marchl 10-14, 2008, pp 1202-1207.

  8. C. Xue, T. Liu, Z. Shao, J. Hu, Z. Jia, W. Jia and E. H.-M. Sha `` Address Assignment Sensitive Variable Partitioning and Scheduling for DSPs with Multiple Memory Banks '' Accepted in Proc. 2008 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Las Vegas, Nevada, USA, pp 1453-1456, March 30 - April 4, 2008.

  9. M. Wang, Z. Shao, H. Liu, C. Xue, `` Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP processors'' Accepted in Proc. IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2008), Milano, Italy, Sept. 2008.

  10. Y. Cao, Z. Shao, M. Wang, C. Xue, Y. Chen, H. Wei, T. Wang `` A Formal Specification and Verification Framework for Designing and Verifying Reliable and Dependable Software for Computerized Numerical Control (CNC) Systems Accepted in Proc. The 28th International Conference on Distributed Computing Systems (ICDCS 2008), Beijing, China, June 17-20, 2008.

  11. C. Xue, Z. Shao, M. Liu, Q. Zhuge and E. H.-M. Sha `` Parallel Network Intrusion Detection on Reconfigurable Platform," Accepted in Proc. 2007 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2007), Lecture Note in Computer Science (LNCS), Springer. Taiwan, Dec 2007

  12. M. Wang, Z. Shao, C. Xue, E. Sha `` Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors," Accepted in Proc. The 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Aug 21-24, 2007 Korea.

  13. G. Hua, M. Wang, Z. Shao, H. Liu, C. Xue `` Real-Time Loop Scheduling with Energy Optimization via DVS and ABB for Multi-Core Embedded Systems," Accepted in Proc. 2007 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2007), Lecture Note in Computer Science (LNCS), Springer. Taiwan, Dec 2007

  14. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha `` Loop Scheduling with Complete Memory Latency Hiding on Multi-core architecture," Accepted in Proc. the 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS), Vol 1, pp. 375-382, July 2006.

  15. M. Qiu, C. Xue, Z. Shao, and E. H.-M. Sha `` Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems," Accepted in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) , Acropolis, Nice, France, April 16-20, 2007

  16. M. Liu, C. Xue, M. Qiu, and E. H.-M. Sha `` Optimizing Timing and Code Size Using Maximum Direct Loop Fusion," Accepted in Proc. The 19th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2006), San Francisco, CA, Sept. 2006.

  17. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha `` Loop Striping: Maximize Parallelism for Nested Loops," Accepted in Proc. 2006 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2006), Lecture Note in Computer Science (LNCS), Springer. Korea, Aug 2006

  18. M. Qiu, C. Xue, Q. Zhuge, Z. Shao, M. Liu, and E. H.-M. Sha `` Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability," Accepted in Proc. IEEE 17th international conference on Application-specific Systems, Architectures and Processors (ASAP), Sep 2006.

  19. M. Qiu, Z. Jia, Z. Shao, C. Xue and E. H.-M. Sha `` Loop Scheduling to Minimize Cost with Data Mining and Prefetching for Heterogeneous DSP," Accepted in Proc. The 18th IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), Dallas, Texas, Nov. 2006.

  20. M. Qiu, C. Xue Z. Shao, M. Liu, and E. H.-M. Sha `` Efficent Algorithm of Energy Minimization for Heterogeneour Wireless Sensor Network," Accepted in Proc. 2006 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2006), Lecture Note in Computer Science (LNCS), Springer. Korea, Aug 2006

  21. M. Qiu, Z. Shao, Qingfeng Zhuge, C. Xue, M. Liu, and E. H.-M. Sha `` Efficient Assignment with Guraranteed Probability for Heterogeneous Parallel DSP," Accepted in Proc. the 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS), July. 2006.

  22. M. Liu, Q. Zhuge, Z. Shao, C. Xue and E. H.-M. Sha `` Loop Distribution and Fusion for Embedded DSP Applications Considering Code Size," Accepted in Proc. The 8th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2005), Las Vegas, Nevada, Dec. 2005.

  23. M. Qiu, M. Liu, C. Xue, Z. Shao, Q. Zhuge and E. H.-M. Sha `` Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems," Accepted in Proc. The 17th IASTED International Conference on Parallel and Distributed Computing Systems, Phoenix, Arizona, Nov. 2005.

  24. C. Xue, Z. Shao, M. Liu, M.K. Qiu and E. H.-M. Sha, `` Optimizing Nested Loops with Iterational and Instructional Retiming," Accepted in Proc. 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2005), Lecture Note in Computer Science (LNCS), Springer. Nagasaki, Japan, 6-9 December 2005

  25. M. Liu, Q. Zhuge, Z. Shao, C. Xue, M. Qiu and E. H.-M. Sha, `` Loop Distribution and Fusion Considering Timing and Code Size for Embedded DSP," Accepted in Proc. The 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC-05), Lecture Note in Computer Science (LNCS), Springer. Nagasaki, Japan, Dec. 2005.

  26. C. Xue, Z. Shao, M. Liu and E. H.-M. Sha, ``Iterational Retiming: Maximize Iteration-Level Parallelism for Nested Loops," Accepted in Proc. The 2005 ACM/IEEE/IFIP International Conference on Hardware - Software Codesign and System Synthesis (ISSS-CODES'05), New York, New York, Sept. 2005.

  27. M. Liu, Z. Shao, C. Xue, K. Chen, E. H.-M. Sha, ``Multi-level Loop Fusion with Minimal Code Size," Accepted in Proc. The 18th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2005), Las Vegas, Sept. 2005.

  28. Y. Chen, Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems," Accepted in Proc. The IEEE/IFIP International Workshop on Parallel and Distributed EMbedded Systems (PDES 2005), in conjunction with ICPADS 2005, Fukuoka, Japan, July 2005(Best workshop paper).

  29. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao, `` Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software", in Proc. IEEE International Conference on Information Technology (ITCC 05), Information Assurance and Security Track , Las Vegas, NV, April 2005.

  30. C. Xue, Z. Shao, Y. Chen and E. H.-M. Sha, ``Optimizing DSP Scheduling via Address Assignment with Array and Loop Transformation", in Proc. 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2005), Philadelphia, PA, March 2005(Winner of the Best Student paper ).

  31. Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``High-level Synthesis for DSP Applications using Heterogeneous Functional Units", in Proc. IEEE Asia and South Pacific Design Automation Conference (ASP DAC 2005), Shanghai, China, Jan. 2005.

  32. C. Xue, Z. Shao, E. H.-M. Sha and B. Xiao, ``Optimizing Address Assignment for Scheduling Embedded DSPs," in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC 2004),, pp. 64-73, Lecture Note in Computer Science (LNCS), Springer, Aizu-Wakamatsu City, Japan, August, 2004.

  33. Z. Shao, Q. Zhuge, Y. He, C. Xue, M. Liu and E. H.-M. Sha, ``Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units," in 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM Proceeding, Santa Fe, Apr. 2004.

  34. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao,`` Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks," In Proc. Information Assurance and Security special track in conjunction with International Conference on Information Technology: Coding and Computing (ITCC 2004), Volume I, pp. 409-413, Las Vegas, Apr. 2004.

Awards

  1. Best Dissertation award (Title: Memory and Parallelism Optimization for Embedded Systems) of Erik Johnson School of Engineering and Computer Science, the University of Texas at Dallas, Jan 2008.

  2. Best paper award (Title: Optimizing DSP Scheduling via Address Assignment with Array and Loop Transformation) in the 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing. A total of 30 Awards are selected from a field of 1400 proceedings, and the only award in the design and implementation of Signal Processing Systems track.

  3. Best paper award (Title: Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems) in the IEEE/IFIP International Workshop on Parallel and Distributed Embedded Systems in conjunction with ICPADS 2005, Fukuoka, Japan, July 2005.

Patent

  1. "Parallel Variable Length Pattern Matching Using Hash Table", Chun Xue, Edwin Sha, Meikang Qiu, Qingfeng Zhuge.
    U. S. Patent, Serial No. 11/307,864, filed Feb 26th, 2006.

  2. "Minimize Energy Consumption Using Optimal Voltage Assignment Algorithm", Meikang Qiu, Edwin H.-M. Sha, Chun Xue, and Qingfeng Zhuge. U. S. Patent, Serial No. 11/307,924, filed Feb 28th, 2006.

Professional Activity

  1. Session Chair, session IIB - Parallel and Distributed Algorithms, ICPADS 2006.

  2. Program Co-Chair, The Fifth IEEE International Symposium on Embedded Computing (SEC), 2008.

  3. Program Co-Chair, The Third International Workshop on Embedded Software Optimization (ESO), 2008.

Education

Ph.D. (2007) Computer Science University of Texas at Dallas
M.S. (2003) Computer Science University of Texas at Dallas
B.S. (1997) Cum Laude Computer Science & Engineering University of Texas at Arlington
B.S. (1997) Magna Cum Laude Architecture University of Texas at Arlington